Ordered Access Memory Based Programmable Hardware Accelerator Parallel Architecture
Rozdział w recenzowanej książce naukowejWspółautorzy: Anatoliy Melnyk
Miejsce: Polyana, Svalyava (Zakarpattya), Ukraine
Rok wydania: 2019
Tytuł publikacji: IEEE 15th International Conference “The Experience of Designing and Application of CAD Systems in Microelectronics” (CADSM'2019)
Strony od-do: 1-5
Streszczenie: Programmable hardware accelerator architecture and information processing method based on a new model of computation with parallel ordered data and command access is proposed in a paper. The principles of the formation, compilation and execution of the computer program in the hardware accelerator according to the proposed model are given. The advantages of the proposed hardware accelerator architecture over traditional ones are highlighted.
Słowa kluczowe: programmable hardware accelerator , parallel architecture , ordered access memory model of computation , high-performance computing
Dostęp WWW: https://ieeexplore.ieee.org/document/8779249
DOI: 10.1109/CADSM.2019.8779249